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FEATURES PERFORMANCE Complete Single-Chip Multiport Internet Gateway Processor (No External Memory Required) Implements Six Modem Channels in One Package Each Processor Can Implement V.34/V.90 Data/Fax Modem (Includes Datapump and Controller) 312 MIPS Sustained Performance, 19 ns Instruction Time @ 3.3 V Open Architecture Extensible to Voice Over IP and Other Applications Low Power Dissipation, 100 mW (Typical) per Digital Modem Processor Power-Down Mode Featuring Low CMOS Standby Power Dissipation INTEGRATION ADSP-2100 Family Code Compatible, with Instruction Set Extensions 960K Bytes of On-Chip RAM, Configured as 576K Bytes of Program Memory and 384K Bytes of Data Memory Dual Purpose Program Memory for Both Instruction and Data Storage 304-Ball PBGA with a 1.45 Square Inch (961 sq. mm) Footprint
Multiport Internet Gateway Processor ADSP-21MOD970
SYSTEM CONFIGURATION 16-Bit Internal DMA Port for High Speed Access to OnChip Memory (Mode Selectable) Programmable Multichannel Serial Port Supports 24 Channels/32 Channels Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Separate RESET Pins for Each Internal Processor GENERAL DESCRIPTION
The ADSP-21MOD970 is a Multiport Internet Gateway Processor optimized for implementation of a complete V.34/56K modem. All data pump and controller functions can be implemented on a single device, offering the lowest power consumption and highest possible modem port density. The ADSP-21MOD970 combines the ADSP-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities and on-chip program and data memory. The ADSP-21MOD970 integrates 960 bytes of on-chip memory, configured as 192K words (24-bit) of program RAM, and 192K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equipment. The ADSP-21MOD970 is available in a 31 sq-mm., 304-lead PBGA package.
FUNCTIONAL BLOCK DIAGRAM
16 DATA<23:8> CLKIN IAD<15:0> IDMA CNTL 16 4 55 27 GROUND VDD
MODEM CHANNEL 2 SPORT0A SPORT1 EMULATOR 4 4 8
MODEM CHANNEL 3
MODEM CHANNEL 4
MODEM CHANNEL 5
MODEM CHANNEL 6 4 SPORT0B
MODEM CHANNEL 1 DATA<23:8>_1 IAD<15:0>_1 CLKIN_1, BUS CNTL_1 IDMA CNTL_1 9 4 16 16
ADSP-21MOD970
IDMA CNTL = IAL, IRD, IWR, IACK FLAGS = FL<0:2>, PF<0:7> BUS CNTL = A0, BMS, PMS, DMS, CMS, IOMS, RD, WR EMULATOR = EMS, EINT, ELIN, EBR, EBG, ECLK, ELOUT, ERESET SPORT0A, SPORT0B = RFS0, DR0, DT0, SCLK0 SPORT1 = RFS1, DR1, SCLK1, TFS1
6 6 6 66 6 6 6 6 6 6
BR<5:0> BG<5:0> BGH<5:0> FLAGS RESET<5:0> CLKOUT<5:0> EE<5:0> IS<5:0> TFS0<5:0> DT1<5:0>
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
ADSP-21MOD970
Fabricated in a high speed, low power, CMOS process, the ADSP-21MOD970 operates with a 19 ns instruction cycle time. Every instruction can execute in a single processor cycle. The ADSP-21MOD970's flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle, the ADSP21mod970 can: * * * * * * * * * Generate the next program address Fetch the next instruction Perform one or two data moves Update one or two data address pointers Perform a computational operation Receive and transmit data through the two serial ports Receive and/or transmit data through the internal DMA port Receive and/or transmit data through the byte DMA port Decrement timer A PROM Splitter generates PROM programmer compatible files. The C Compiler, based on the Free Software Foundation's GNU C Compiler, generates ADSP-21MOD970 assembly source code. The source code debugger allows programs to be corrected in the C environment. The Runtime Library includes over 100 ANSI-standard mathematical and DSP-specific functions. The ADSP-218x EZ-ICE(R) Emulator aids in the hardware debugging of an ADSP-21MOD970 system. The EZ-ICE, in conjunction with the required processor selection hardware, lets you independently debug code on individual modem processors. The emulator consists of hardware, host computer resident software, and the target board connector. The ADSP-21MOD970 integrates on-chip emulation support with a 14-pin ICE-PortTM interface. The ADSP-21MOD970 device need not be removed from the target system when using the EZ-ICE, nor are any adapters needed. Due to the small footprint of the EZ-ICE connector, emulation can be supported in final board designs. The EZ-ICE performs a full range of functions, including: * * * * * * * * In-target operation Up to 20 breakpoints Single-step or full-speed operation Registers and memory values can be examined and altered PC upload and download functions Instruction-level emulation of program booting and execution Complete assembly and disassembly of instructions C source-level debugging
This takes place while the processor continues to:
Modem Software
The modem software executes general modem control, command sets, error correction and data compression, data modulations (for example, V.90 and V.34), and host interface functions. The host interface allows system access to modem statistics such as call progress, connect speed, retrain count, symbol rate and other modulation parameters. The modem data pump and controller software reside in onchip SRAM and do not require additional memory. The user can configure the ADSP-21MOD970 dynamically by downloading software from the host through the 16-bit DMA interface. This SRAM-based architecture provides a software upgrade path to future standards and applications, such as voice over IP. The modem software is available as object code.
DEVELOPMENT SYSTEM
See "Designing An EZ-ICE-Compatible Target System" in the ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as well as the Designing an EZ-ICE Compatible System section of this data sheet for the exact specifications of the EZ-ICE target board connector.
Additional Information
The ADSP-2100 Family Development Software, a complete set of tools for software and hardware system development, supports the ADSP-21MOD970. The System Builder provides a high level method for defining the architecture of systems under development. The Assembler has an algebraic syntax that is easy to program and debug. The Linker combines object files into an executable file. The Simulator provides an interactive instructionlevel simulation with a reconfigurable user interface to display different portions of the hardware environment.
This data sheet provides a general overview of ADSP-21MOD970 functionality. For specific information about the modem processors, refer to the ADSP-21mod870 data sheet. For additional information on the architecture and instruction set of the modem processors, refer to the ADSP-2100 Family User's Manual, Third Edition. For more information about the development tools, refer to the ADSP-2100 Family Development Tools Data Sheet.
EZ-ICE is a registered trademark of Analog Devices, Inc. ICE-Port is a trademark of Analog Devices, Inc.
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ARCHITECTURE OVERVIEW
Figure 1 is an overall block diagram of the ADSP-21MOD970 modem pool. The modem pool contains six independent digital modem processors. Each individual modem processor has a DSP core, 160K bytes of RAM, two serial ports, and a DMA port. The signals for a single processor are shown in Figure 2. The signals of each modem processor are accessed through the external pins of the ADSP-21MOD970. Some signals are bused with the signals of the other processors and are accessed through a single external pin. Other signals remain separate and they are accessed through separate external pins for each processor. The arrangement of the six modem processors in the ADSP21mod970 makes two basic configurations possible: a master configuration and a slave configuration. In both configurations, the control and data pins of five of the six processors connect to a single bus structure. The control and data pins of the one modem processor (Modem Processor 1) are separate from the other modem processors and accessed through external pins. In Slave Mode, all six modem processors have identical functions and have equal status. Each modem processor is connected to a common DMA bus and each modem processor is configured to operate in the same mode (see the Slave Mode and the Memory Mode descriptions in the Memory Architecture
INDIVDUAL SIGNALS
MODEM PROCESSOR
PF7/IRQ2 DATA 23:8 PF6/IRQ1 IAD 15:0 IAL PF5/IRQ0 IRD PF4/IRQE IRW PF3/MODE D IACK PF2/MODE C PF1/MODE B DATA 23:8 PF0/MODE A IAD 15:0 FL2 IAL MODEM FL1 IRD PROCESSOR 1 FL0 IRW EE IACK IS EMS TFS0 EINT DT1 ELIN BGH EBR BG EBG BR ECLK ELOUT CLKOUT ERESET RESET RFS0 A0 DR0 BMS DT0 PMS SCLK0 MODEM DMS PROCESSOR 1 RFS1 CMS (ONLY) DR1 IOMS TFS1 RD SCLK1 WR CLKIN
BUSED SIGNALS
Figure 2. Modem Processor Signals
ADSP-21MOD970
16 DATA<23:8> CLKIN IAD<15:0> IDMA CNTL 16 4
MODEM CHANNEL 2 SPORT0A SPORT1 EMULATOR 4 4 8
MODEM CHANNEL 3
MODEM CHANNEL 4
MODEM CHANNEL 5
MODEM CHANNEL 6 4 SPORT0B
MODEM CHANNEL 1 DATA<23:8> IAD<15:0> CLKIN_1, BUS CNTL IDMA CNTL 16 16 9 4
IDMA CNTL = IAL, IRD, IWR, IACK FLAGS = FL<0:2>, PF<0:7> BUS CNTL = A0, BMS, PMS, DMS, CMS, IOMS, RD, WR EMULATOR = EMS, EINT, ELIN, EBR, EBG, ECLK, ELOUT, ERESET SPORT0A, SPORT0B = RFS0, DR0, DT0, SCLK0 SPORT1 = RFS1, DR1, SCLK1, TFS1 THE FOLLOWING SIGNALS ARE ROUTED TO EACH ADSP-21MOD970: BR<5:0> BG<5:0> BGH<5:0> FLAGS RESET<5:0> CLKOUT<5:0> EE<5:0> IS<5:0> TFS0<5:0> DT1<5:0> 6 6 6 66 6 6 6 6 6 6 GND VDD 55 27
NOTES: IRQ FUNCTIONS ARE MULTIPLEXED WITH PROGRAMMABLE FLAGS (SEE ADSP-21mod870 DATA SHEET)
Figure 1. Modem Pool
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section). The Slave Mode is considered to be the normal mode of operation in a modem pool application. Figure 3 shows the modem pool configured for slave mode operation. The master mode of the ADSP-21MOD970 configures five of the modem processors with identical functions and isolates one of the modem processors, Processor 1. In the Master Mode, Processor 1 is not connected to the DMA bus as are the other five modem processors. Processor 1 operates in a different mode where external pins can be used for access to a 16-bit data bus, a 14-bit address bus with associated bus control pins. In master
6 6 6 6 6 42 MODE A MODE B MODE C MODE D SPORT0 ICE SPORT0 ICE SPORT0 ICE BUS ICE SPORT0 ICE SPORT0 ICE SPORT0 ICE SPORT0B BUS 4 14 SPORT0A BUS
mode, Processor 1 is treated as a master of the modem pool and communicates with an external device such as a RAM, ROM or a memory shared with a host processor. In this configuration, the master processor performs some controlling function of the remaining five modem processors. Figure 4 shows the modem pool configured for Slave Mode operation. Since the memory bus of Processor 1 is accessible via external pins in master mode, Processor 1 can be configured for one of the several memory modes available on the ADSP-21xx family. (See Full Memory, Host Mode Descriptions.)
CLKOUT RESET BR BG BGH FLAGS HIGH/1 LOW/0 HIGH/1 HIGH/1
ADSP-21MOD970
4 SPORT0A SPORT0B ICE
MODE A MODE B MODE C MODE D
HIGH/1 LOW/0 HIGH/1 HIGH/1 5
MODEM PROCESSOR 1 (MASTER) CNTL ADDR
MODEM PROCESSOR 2 (SLAVE) D&CB IDMA
MODEM PROCESSOR 3 (SLAVE) D&CB IDMA
MODEM PROCESSOR 4 (SLAVE) D&CB IDMA
MODEM PROCESSOR 5 (SLAVE) D&CB IDMA
MODEM PROCESSOR 6 (SLAVE) D&CB IDMA
IDMA DATA & CONTROL BUS CLKIN
21 24
25 16
IDMA DATA BUS CLKIN
Figure 3. Configured for Slave Mode
CLKOUT RESET BR BG BGH FLAGS HIGH/1 LOW/0 HIGH/1 HIGH/1
6 6 6 6 SPORT0B BUS 6 42 MODE A MODE B MODE C MODE D SPORT0 ICE SPORT0 ICE SPORT0 ICE BUS ICE SPORT0 ICE SPORT0 ICE SPORT0 ICE 4 14 SPORT0A BUS
ADSP-21MOD970
4 SPORT0A SPORT0B ICE
MODE A MODE B MODE C MODE D
HIGH/1 LOW/0 HIGH/1 HIGH/1 5
MODEM PROCESSOR 1 (MASTER) CNTL ADDR
MODEM PROCESSOR 2 (SLAVE) D&CB IDMA
MODEM PROCESSOR 3 (SLAVE) D&CB IDMA
MODEM PROCESSOR 4 (SLAVE) D&CB IDMA
MODEM PROCESSOR 5 (SLAVE) D&CB IDMA
MODEM PROCESSOR 6 (SLAVE) D&CB IDMA
CONTROL ADDRESS MASTER DATA CLKIN
7 14 24
25 16
IDMA DATA BUS CLKIN
Figure 4. Configured for Master Mode
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Serial Ports Common-Mode Pins Pin Name(s) RESET BR BG BGH DMS PMS BMS IOMS CMS RD WR IRQ2/ PF7 IRQL1/ PF6 IRQL0/ PF5 IRQE/ PF4 Mode D/ PF3 Mode C/ PF2 Mode B/ PF1 Mode A/ PF0 CLKIN CLKOUT SPORT FL0, FL1, FL2 VDD and GND 2 6 24 18 82 6 6 6 # Input/ of OutPins put Function 6 6 6 6 1 1 1 I 1 1 1 6 I I O O O O O O O O O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I O I/O O I Processor Reset Input Bus Request Input Bus Grant Output Bus Grant Hang Output Data Memory Select Output Program Memory Select Output Byte Memory Select Output I/O Memory Select Output Combined Memory Select Output Memory Read Enable Output Memory Write Enable Output Edge- or Level-Sensitive Interrupt Request1 Programmable I/O Pin Level-Sensitive Interrupt Requests 1 Programmable I/O Pin Level-Sensitive Interrupt Requests 1 Programmable I/O Pin Edge-Sensitive Interrupt Requests 1 Programmable I/O Pin Mode Select Input--Checked Only During RESET Programmable I/O Pin During Normal Operation Mode Select Input--Checked Only During RESET Programmable I/O Pin During Normal Operation Mode Select Input--Checked Only During RESET Programmable I/O Pin During Normal Operation Mode Select Input--Checked Only During RESET Programmable I/O Pin During Normal Operation Clock Input Processor Clock Output Serial Port I/O Pins2 Output Flags Power and Ground
The ADSP-21MOD970 has a multichannel serial port (SPORT) connected to each internal digital modem processor for serial communications. Following is a brief list of the capabilities of the ADSP-21MOD970 SPORT. For additional information on the internal Serial Ports, refer to the ADSP-2100 Family User's Manual, Third Edition. * * * SPORT is bidirectional and has a separate, double-buffered transmit and receive section. SPORT can use an external serial clock or generate its own serial clock internally. SPORT has independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame synchronization signals internally or externally generated. Frame sync signals are active high or inverted, with either of two pulsewidths and timings. SPORT supports serial data word lengths from 3 to 16 bits and provides optional A-law and -law companding according to CCITT recommendation G.711. SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer. SPORT can receive and transmit an entire circular buffer of data with one overhead cycle per data word. An interrupt is generated after a data buffer transfer. A multichannel interface selectively receives and transmits a 24- or 32-word, time-division multiplexed, serial bitstream.
*
* *
6 6 6 6
*
PIN DESCRIPTIONS
The ADSP-21MOD970 is available in a 304-lead PBGA package. In order to maintain maximum functionality and reduce package size and pin count, some serial port, programmable flag, interrupt and external bus pins have dual, multiplexed functionality. The external bus pins are configured during RESET only, while serial port pins are software configurable during program execution. Flag and interrupt functionality is retained concurrently on multiplexed pins. In cases where pin functionality is reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics.
EZ-Port
14
I/O
For Emulation Use
NOTES 1 Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the modem pool will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag. 2 SPORT configuration determined by the modem pool's System Control Register. Software configurable.
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Memory Interface Pins Table I. Interrupt Priority and Interrupt Vector Addresses
The ADSP-21MOD970 modem pool can be used in one of two modes, master mode or slave mode. In master mode, Modem Processor 1 operates with full memory (BDMA operation with full external overlay memory and I/O capability). In Slave Mode, Modem Processor 1 operates in host configuration (IDMA operation with limited external addressing capabilities). The operating mode is determined by the state of the Mode C pin during RESET and cannot be changed while the modem pool is running. See the Memory Architecture section for more information.
Full Memory Pins (Mode C = 0) Modem Processor 1 Only
Source Of Interrupt RESET (or Power-Up with PUCR = 1) Power-Down (Nonmaskable) IRQ2 IRQL1 IRQL0 SPORT0 Transmit SPORT0 Receive IRQE BDMA Interrupt SPORT1 Transmit or IRQ1 SPORT1 Receive or IRQ0 Timer
Interrupt Vector Address (Hex) 0000 (Highest Priority) 002C 0004 0008 000C 0010 0014 0018 001C 0020 0024 0028 (Lowest Priority)
Pin Name A13:0 D23:0
# of Input/ Pins Output Function 14 24 O I/O Address Output Pins for Program, Data, Byte and I/O Spaces Data I/O Pins for Program, Data, Byte and I/O Spaces (8 MSBs Are Also Used as Byte Memory Addresses)
When the modem pool is reset, interrupt servicing is disabled.
LOW POWER OPERATION
The ADSP-21MOD970 has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions. These modes are: * Power-Down * Idle * Slow Idle The CLKOUT pin may also be disabled to reduce external power dissipation.
Power-Down
Host Pins (Mode C = 1)* Modem Processor 1 and Modem Processors 2-6
Pin Name
# of Input/ Pins Output Function I/O O IDMA Port Address/Data Bus Address Pin for External I/O, Program, Data, or Byte Access (Modem Processor 1 Only) Data I/O Pins for Program, Data Byte and I/O Spaces IDMA Write Enable IDMA Read Enable IDMA Address Latch Pin IDMA Select IDMA Port Acknowledge Configurable in Mode D; Open Drain
IAD15:0 32 A0 1
D23:8 IWR IRD IAL IS IACK
32 2 2 2 6 2
I/O I I I I O
The ADSP-21MOD970 modem pool has a low power feature that lets the modem pool enter a very low power dormant state through software control. Following is a brief list of power-down features. Refer to the ADSP-2100 Family User's Manual, Third Edition, "System Interface" chapter, for detailed information about the power-down feature. * * Quick recovery from power-down. The modem pool begins executing instructions in as few as 400 CLKIN cycles. Support for an externally generated TTL or CMOS processor clock. The external clock can continue running during power-down without affecting the lowest power rating and 400 CLKIN cycle recovery. Power-down is initiated by the software power-down force bit. Interrupt support allows an unlimited number of instructions to be executed before optionally powering down. The power-down interrupt also can be used as a nonmaskable, edge-sensitive interrupt. Context clear/save control allows the modem pool to continue where it left off or start with a clean context when leaving the power-down state. The RESET pin also can be used to terminate power-down.
*In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, BMS and IOMS signals of Modem Processor 1.
*
Interrupts
The interrupt controller allows each modem processor in the modem pool to respond individually to eleven possible interrupts and reset with minimum overhead. The ADSP-21MOD970 provides four dedicated external interrupt input pins, IRQ2, IRQL1, IRQL0, and IRQE (shared with the PF7:4 pins) for each modem processor. The ADSP-21MOD970 also supports internal interrupts from the timer, the byte DMA port, the serial port, software and the power-down control circuit. The interrupt levels are internally prioritized and individually maskable (except power-down and reset). The IRQ2, IRQL1, and IRQL0 input pins can be programmed to be either level- or edge-sensitive. IRQL0 and IRQL1 are level-sensitive and IRQE is edge sensitive. The priorities and vector addresses of all interrupts are shown in Table I.
*
*
Idle
When the ADSP-21MOD970 is in the idle mode, the modem pool waits indefinitely in a low power state until an interrupt occurs. When an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the IDLE instruction. In idle mode IDMA, BDMA and autobuffer cycle steals still occur.
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Slow Idle
The IDLE instruction is enhanced on the ADSP-21MOD970 to let the modem pool's internal clock signal be slowed, further reducing power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the IDLE instruction. The format of the instruction is IDLE (n); where n = 16, 32, 64 or 128. This instruction keeps the modem pool fully functional, but operating at the slower clock rate. While it is in this state, the modem pool's other internal clock signals, such as SCLK, CLKOUT and timer clock, are reduced by the same ratio. The default form of the instruction, when no clock divisor is given, is the standard IDLE instruction. When the IDLE (n) instruction is used, it effectively slows down the modem pool's internal clock and thus its response time to incoming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an enabled interrupt is received, the ADSP-21MOD970 will remain in the idle state for up to a maximum of n modem pool cycles (n = 16, 32, 64 or 128) before resuming normal operation. When the IDLE (n) instruction is used in systems that have an externally generated serial clock (SCLK), the serial clock rate may be faster than the modem pool's reduced internal clock rate. Under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the modem pool takes to come out of the idle state (a maximum of n cycles).
SYSTEM CONFIGURATION
the host access server data directly from the ADSP-21MOD970's internal memory. In this configuration, the Modem Processor 1 should be put into host memory mode where Mode D = 1, Mode C = 1, Mode B = 0, and Mode A = 1 (see Table II).
CLOCK SIGNALS
The ADSP-21MOD970 is clocked by a TTL-compatible clock signal that runs at half the instruction rate; a 26 MHz input clock yields a 19 ns processor cycle (which is equivalent to 52 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction clock rate, which is indicated by the CLKOUT signal when enabled. The clock input signal is connected to the processor's CLKIN input. The CLKIN input cannot be halted, changed during operation, or operated below the specified frequency during normal operation. The only exception is while the processor is in the powerdown state. For additional information, refer to Chapter 9, ADSP-2100 Family User's Manual, Third Edition, for a detailed explanation of this power-down feature. A clock output (CLKOUT) signal is generated by the processor at the processor's cycle rate.
Reset
The RESET signals initiate a reset of each modem processor in the ADSP-21MOD970. The RESET signals must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to let the internal clocks stabilize. If RESETs are activated any time after power-up, the clocks continue to run and do not require stabilization time. The power-up sequence is defined as the total time required for the oscillator circuits to stabilize after a valid VDD is applied to the processors, and for the internal phase-locked loops (PLL) to lock onto the specific frequency. A minimum of 2000 CLKIN cycles ensures that the PLLs have locked, but this does not include the oscillators start-up time. During this power-up sequence, the RESET signals should be held low. On any subsequent resets, the RESET signals must meet the minimum pulsewidth specification, tRSP.
Figure 5 shows a typical multichannel modem configuration with the ADSP-21MOD970. A line interface can be used to connect the multichannel subscriber or client data stream to the multichannel serial port of the ADSP-21MOD970. The ADSP21mod970 can support up to 64 channels. The IDMA port of the ADSP-21MOD970 is used to give a host processor full access to the internal memory of the ADSP-21MOD970. This lets the host dynamically configure the ADSP-21MOD970 by loading code and data into its internal memory. This configuration also lets
T1/E1 LINE INTERFACE SPORT
SPORT
SPORT
SPORT
ADSP-21MOD970
(SLAVE MODE) ST/CNTL STATUS & CONTROL HOST CONTROL HOST MICRO HOST ADDRESS HOST DATA STATUS & CONTROL PAL IDMA CONTROL IDMA PAL IDMA ADDRESS IDMA
ADSP-21MOD970
(SLAVE MODE) ST/CNTL IDMA
ADSP-21MOD970
(SLAVE MODE) ST/CNTL IDMA
ADSP-21MOD970
(SLAVE MODE) ST/CNTL IDMA
Figure 5. Multichannel Modem Configuration
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The RESET inputs contain some hysteresis; however, if an RC circuit is used to generate the RESET signals, the use of external Schmidt triggers are recommended. The reset for each individual modem processor sets the internal stack pointers to the empty stack condition, masks all interrupts and clears the MSTAT register. When a RESET is released, if there is no pending bus request and the modem processor is configured for booting, the boot-loading sequence is performed. The first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes.
MEMORY ARCHITECTURE
Memory and I/O. Refer to the figures and tables below for PM and DM memory allocations in the ADSP-21MOD970. The ADSP-21MOD970 modem pool operates in one of two memory modes: Slave Mode or Master Mode. The memory modes determine the memory access to Modem Processor 1. In Slave Mode, the memory of Modem Processor 1 is configured for Host Mode; in Master Mode, the memory of Modem Processor 1 is configured for Full-Memory Mode. Memories for Modem Processors 2-6 are configured only for Host Mode. The differences between these memory modes are explained in the following sections. Figure 6 shows Program Memory, while Figure 7 shows Data Memory. Table II summarizes ADSP21mod970 operating modes. Table III explains the mode bits and memory booting.
The ADSP-21MOD970 provides a variety of memory and peripheral interface options for Modem Processor 1. The key functional groups are Program Memory, Data Memory, Byte
MODE B = 0 ALWAYS ACCESSIBLE AT ADDRESS 0x0000 - 0x1FFF 0x2000- ACCESSIBLE WHEN 0x3FFF PMOVLAY = 0 0x2000- 0x3FFF 0x2000- ACCESSIBLE WHEN 0x3FFF INTERNAL PMOVLAY = 4 0x2000- MEMORY ACCESSIBLE WHEN 0x3FFF PMOVLAY = 5 0x2000- ACCESSIBLE WHEN 0x3FFF EXTERNAL PMOVLAY = 1 MEMORY ACCESSIBLE WHEN PMOVLAY = 2 PMOVLAY 0, 4, 5 1 2 MEMORY INTERNAL EXTERNAL OVERLAY1 EXTERNAL OVERLAY2 A13* NOT APPLICABLE 0 1 A12:0* NOT APPLICABLE 13 LSBs OF ADDRESS BETWEEN 0x2000 AND 0x3FFF 13 LSBs OF ADDRESS BETWEEN 0x2000 AND 0x3FFF PROGRAM MEMORY ADDRESS MODE B = 0 8K INTERNAL PMOVLAY = 0, 4, 5 OR 8K EXTERNAL PMOVLAY = 1, 2 0x3FFF
DATA MEMORY ALWAYS ACCESSIBLE AT ADDRESS 0x2000 - 0x3FFF 0x0000- ACCESSIBLE WHEN 0x1FFF DMOVLAY = 0 0x0000- 0x1FFF 0x0000- ACCESSIBLE WHEN 0x1FFF INTERNAL DMOVLAY = 4 0x0000- MEMORY ACCESSIBLE WHEN 0x1FFF DMOVLAY = 5 0x0000- ACCESSIBLE WHEN 0x1FFF EXTERNAL DMOVLAY = 1 MEMORY ACCESSIBLE WHEN DMOVLAY = 2 PMOVLAY 0, 4, 5 1 2 MEMORY INTERNAL EXTERNAL OVERLAY1 EXTERNAL OVERLAY2 A13* NOT APPLICABLE 0 1
DATA MEMORY 32 MEMORY MAPPED REGISTERS
ADDRESS 0x3FFF
0x2000 0x1FFF
0x3FE0 0x3FDF INTERNAL 8160 WORDS 0x2000 0x1FFF
8K INTERNAL 0x0000
8K INTERNAL DMOVLAY = 0, 4, 5 OR 8K EXTERNAL DMOVLAY = 1, 2
0x0000
A12:0* NOT APPLICABLE 13 LSBs OF ADDRESS BETWEEN 0x2000 AND 0x3FFF 13 LSBs OF ADDRESS BETWEEN 0x2000 AND 0x3FFF
*FULL-MEMORY MODE ONLY
*FULL-MEMORY MODE ONLY
Figure 6. Program Memory (Memory Shown in Grey Is Accessible Only in Full-Memory Mode)
Figure 7. Data Memory
Table II. Processor and Memory Mode
Memory Modes for Modem Processor 1 Host
ADSP-21MOD970 Modes Master * All Internal Program Memory Available * All Internal Data Memory Available * IDMA Port Enabled * All Internal and External Program Memory Available * All Internal and External Data Memory Available * I/O Space Available * Byte Memory DMA (BDMA) Enabled Slave * All Internal Program Memory Available * All Internal Data Memory Available * IDMA Port Enabled Not Applicable
Full-Memory
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Table III. Modes of Operation
MODE D X
MODE C 0
MODE B 0
MODE A 0
Booting Method BDMA feature is used to load the first 32 program memory words from byte memory space. Program execution is held off until all 32 words are loaded. Chip is configured in Full-Memory Mode1 BDMA feature is used to load the first 32 program memory words from byte memory space. Program execution is held off until all 32 words are loaded. Chip is configured in Host Mode. IACK requires pull-down. (REQUIRES ADDITIONAL HARDWARE.) IDMA feature is used to load internal memory as desired. Program execution is held off until internal program memory location 0x0000 is written to. Chip is configured in Host Mode.1 IACK requires pull-down. BDMA feature is used to load the first 32 program memory words from byte memory space. Program execution is held off until all 32 words are loaded. Chip is configured in Host Mode. IACK requires external pulldown. (REQUIRES ADDITIONAL HARDWARE.) IDMA feature is used to load internal memory as desired. Program execution is held off until internal program memory location 0x0000 is written to. Chip is configured in Host Mode.1 IACK requires external pull-down.1
0
1
0
0
0
1
0
1
1
1
0
0
1
1
0
1
NOTE 1 Considered standard operating settings. These configurations simplify your design and improve memory management.
Slave Mode
This section describes the Slave Mode memory configuration of Modem Processor 1. Modem Processors 2-6 are always configured for Slave Mode. Program Memory (Host Mode) allows access to all internal memory. External overlay access is limited by a single external address line (A0). External program execution is not available in host mode due to a restricted data bus that is 16-bits wide only. Data Memory (Host Mode) allows access to all internal memory. External overlay access is limited by a single external address line (A0).
Internal Memory DMA Port (IDMA Port; Host Memory Mode)
5. Host checks IACK line to see if the processor has completed the previous IDMA operation. 6. Host ends IDMA transfer. The IDMA port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. The IDMA port is completely asynchronous and can be written to while the ADSP21mod970 is operating at full speed. The processor memory address is latched and then automatically incremented after each IDMA transaction. An external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. This increases throughput as the address does not have to be sent for each memory access. IDMA Port access occurs in two phases. The first is the IDMA Address Latch cycle. When the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. The address specifies an on-chip memory location, the destination type specifies whether it is a DM or PM access. The falling edge of the address latch signal latches this value into the IDMAA register. Once the address is stored, data can then either be read from or written to, the ADSP-21MOD970's on-chip memory. Asserting the select line (IS) and the appropriate read or write line (IRD and IWR respectively) signals the ADSP-21MOD970 that a particular transaction is required. In either case, there is a oneprocessor-cycle delay for synchronization. The memory access consumes one additional processor cycle. Once an access has occurred, the latched address is automatically incremented, and another access can occur. Through the IDMAA register, the processor can also specify the starting address and data format for DMA operation. Asserting the IDMA port select (IS) and address latch enable (IAL) directs the ADSP-21MOD970 to write the address onto the
The IDMA Port provides an efficient way for a host system and the ADSP-21MOD970 to communicate. The port is used to access the on-chip program memory and data memory of each modem processor with only one processor cycle per word overhead. The IDMA port cannot be used, however, to write to the processor's memory-mapped control registers. A typical IDMA transfer process is described as follows: 1. Host starts IDMA transfer. 2. Host checks IACK control line to see if the processor is busy. 3. Host uses IS and IAL control lines to latch either the DMA starting address (IDMAA) or the PM/DM OVLAY selection into the processor's IDMA control registers. If IAD [15] = 1, the value of IAD [7:0] represent the IDMA overlay: IAD [14:8] must be set to 0. If IAD [15] = 0, the value of IAD [13:0] represent the starting address of internal memory to be accessed and IAD [14] reflects PM or DM for access. 4. Host uses IS and IRD (or IWR) to read (or write) processor internal memory (PM or DM).
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IAD0[14.0] bus into the IDMA Control Register. If IAD[15] is set to 0, IDMA latches the address. If IAD[15] is set to 1, IDMA latches OVLAY memory. The IDMAA register is memory mapped at address DM (0x3FE0). Note that the latched address (IDMAA) cannot be read back by the host. The IDMA Overlay Register is memory mapped at address DM (0x3FE7). See Figure 8 for more information on IDMA memory maps.
DMA PROGRAM MEMORY OVLAY ALWAYS ACCESSIBLE AT ADDRESS 0x2000 - 0x3FFF 0x2000- ACCESSIBLE WHEN 0x3FFF PMOVLAY = 0 0x2000- 0x3FFF ACCESSIBLE WHEN PMOVLAY = 4 ACCESSIBLE WHEN PMOVLAY = 5 0x2000- 0x3FFF DMA DATA MEMORY OVLAY ALWAYS ACCESSIBLE AT ADDRESS 0x2000 - 0x3FFF 0x0000- ACCESSIBLE WHEN 0x1FFF DMOVLAY = 0 0x0000- 0x1FFF ACCESSIBLE WHEN DMOVLAY = 4 ACCESSIBLE WHEN DMOVLAY = 5 0x0000- 0x1FFF
I/O Space (Full Memory Mode)
The ADSP-21MOD970 supports an additional external memory space called I/O space. This space is designed to support simple connections to peripherals (such as data converters and external registers) or to bus interface ASIC data registers. I/O space supports 2048 locations of 16-bit wide data. The lower eleven bits of the external address bus are used; the upper three bits are undefined. Two instructions were added to the core ADSP-2100 Family instruction set to read from and write to I/O memory space. The I/O space also has four dedicated three-bit wait state registers, IOWAIT0-3, which specify up to seven wait states to be automatically generated for each of four regions. The wait states act on address ranges as shown in Table IV.
Table IV. Wait States
Address Range 0x000-0x1FF 0x200-0x3FF 0x400-0x5FF 0x600-0x7FF
Wait State Register IOWAIT0 IOWAIT1 IOWAIT2 IOWAIT3
NOTE: IDMA AND BDMA HAVE SEPERATE DMA CONTROL REGISTERS IDMA OVERLAY 9 8 7 6 0 0 0 0
15
14 0
13 0
12 0
11 0
10 0
5 0
4 0
3 0
2 0
1 0
0 0 DM (0x3FE7)
Byte Memory
RESERVED SET TO 0
ID DMOVLAY
ID PMOVLAY
15
14 U
13 U
IDMA CONTROL (U = UNDEFINED AT RESET) 12 11 10 9 8 7 6 5 4 3 U U U U U U U U U U
2 U
1 U
0 U DM (0x3FE0)
The byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. Byte memory is accessed using the BDMA feature. The byte memory space consists of 256 pages, each of which is 16K x 8. The byte memory space on the ADSP-21MOD970 supports read and write operations as well as four different data formats. The byte memory uses data bits 15:8 for data. The byte memory uses Data Bits 23:16 and Address Bits 13:0 to create a 22-bit address. This allows up to a 4 meg x 8 (32 megabit) ROM or RAM to be used without glue logic. All byte memory accesses are timed by the BMWAIT register.
Byte Memory DMA (BDMA, Full Memory Mode)
IDMAD DESTINATION MEMORY TYPE: 0 = PM 1 = DM
IDMAA ADDRESS
Figure 8. IDMA Control/OVLAY Registers
IDMA Port Booting
The ADSP-21MOD970 can also boot programs through its Internal DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the ADSP-21MOD970 boots from the IDMA port. IDMA feature can load as much on-chip memory as desired. Program execution is held off until on-chip program memory location 0 is written to.
Master Mode
The byte memory DMA controller allows loading and storing of program instructions and data using the byte memory space. The BDMA circuit can access the byte memory space while the processor is operating normally and steals only one processor cycle per 8-, 16- or 24-bit word transferred. The BDMA circuit supports four different data formats that are selected by the BTYPE register field. The appropriate number of 8-bit accesses are done from the byte memory space to build the word size selected. Table V shows the data formats supported by the BDMA circuit.
Table V. Data Formats
This section describes the Master Mode memory configuration of Modem Processor 1. Master Mode is not available for Modem Processors 2-6. Program Memory (Full Memory Mode) is a 24-bit-wide space for storing both instruction op codes and data. The ADSP-21MOD970 has 32K words of Program Memory RAM on chip, and it can access up to two 8K external memory overlay spaces using the external data bus. Data Memory (Full Memory Mode) is a 16-bit-wide space used for the storage of data variables and for memory-mapped control registers. The ADSP-21MOD970 has 32K words on Data Memory RAM on chip, consisting of 16,352 user-accessible locations and 32 memory-mapped registers. The ADSP-21MOD970 also supports up to two 8K external memory overlay spaces through the external data bus. All internal accesses complete in one cycle. Accesses to external memory are timed using the wait states specified by the DWAIT register.
BTYPE 00 01 10 11
Internal Memory Space Program Memory Data Memory Data Memory Data Memory
Word Size 24 16 8 8
Alignment Full Word Full Word MSBs LSBs
Unused bits in the 8-bit data memory formats are filled with 0s. The BIAD register field is used to specify the starting address for the on-chip memory involved with the transfer. The 14-bit BEAD register specifies the starting address for the external byte
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memory space. The 8-bit BMPAGE register specifies the starting page for the external byte memory space. The BDIR register field selects the direction of the transfer. Finally the 14-bit BWCOUNT register specifies the number of DSP words to transfer and initiates the BDMA circuit transfers. BDMA accesses can cross page boundaries during sequential addressing. A BDMA interrupt is generated on the completion of the number of transfers specified by the BWCOUNT register. The BWCOUNT register is updated after each transfer so it can be used to check the status of the transfers. When it reaches zero, the transfers have finished and a BDMA interrupt is generated. The BMPAGE and BEAD registers must not be accessed by the processor during BDMA operations. The source or destination of a BDMA transfer will always be on-chip program or data memory. When the BWCOUNT register is written with a nonzero value the BDMA circuit starts executing byte memory accesses with wait states set by BMWAIT. These accesses continue until the count reaches zero. When enough accesses have occurred to create a destination word, it is transferred to or from on-chip memory. The transfer takes one processor cycle. Processor accesses to external memory have priority over BDMA byte memory accesses. The BDMA Context Reset bit (BCR) controls whether the processor is held off while the BDMA accesses are occurring. Setting the BCR bit to 0 allows the processor to continue operations. Setting the BCR bit to 1 causes the processor to stop execution while the BDMA accesses are occurring, to clear the context of the processor, and start execution at Address 0 when the BDMA accesses have completed. The BDMA overlay bits specify the OVLAY memory blocks to be accessed for internal memory.
Bootstrap Loading (Booting)
The ADSP-2100 Family development software (Revision 5.02 and later) fully supports the BDMA booting feature and can generate byte memory space compatible boot code. The IDLE instruction can also be used to allow the processor to hold off execution while booting continues through the BDMA interface. For BDMA accesses while in Host Mode, the addresses to boot memory must be constructed externally to the ADSP21mod970. The only memory address bit provided by the processor is A0.
Composite Memory Select (CMS)
The ADSP-21MOD970 has a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space. The CMS signal is generated to have the same timing as each of the individual memory select signals (PMS, DMS, BMS, IOMS) but can combine their functionality. Each bit in the CMSSEL register, when set, causes the CMS signal to be asserted when the selected memory select is asserted. For example, to use a 32K word memory to act as both program and data memory, set the PMS and DMS bits in the CMSSEL register and use the CMS pin to drive the chip select of the memory, and use either DMS or PMS as the additional address bit. The CMS pin functions like the other memory select signals with the same timing and bus request logic. A 1 in the enable bit causes the assertion of the CMS signal at the same time as the selected memory select signal. All enable bits default to 1 at reset, except the BMS bit.
Boot Memory Select (BMS) Disable
The ADSP-21MOD970 has two mechanisms to allow automatic loading of the internal program memory after reset. The method for booting is controlled by the Mode A, B and C configuration bits. When the MODE pins specify BDMA booting, the ADSP21mod970 initiates a BDMA boot sequence when reset is released. The BDMA interface is set up during reset to the following defaults when BDMA booting is specified: the BDIR, BMPAGE, BIAD and BEAD registers are set to 0, the BTYPE register is set to 0 to specify program memory 24-bit words, and the BWCOUNT register is set to 32. This causes 32 words of onchip program memory to be loaded from byte memory. These 32 words are used to set up the BDMA to load in the remaining program code. The BCR bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into on-chip program memory. Execution then begins at Address 0.
The ADSP-21MOD970 also lets you boot the processor from one external memory space while using a different external memory space for BDMA transfers during normal operation. You can use the CMS to select the first external memory space for BDMA transfers and BMS to select the second external memory space for booting. The BMS signal can be disabled by setting Bit 3 of the System Control Register to 1. The System Control Register is illustrated in Figure 9.
Bus Request and Bus Grant
Each modem processor in the ADSP-21MOD970 can relinquish control of the data and address buses to an external device. When the external device requires access to memory, it asserts the bus request (BR) signal. If the modem processor is not performing an external memory access, then it responds to the active BR input in the following processor cycle by: * * * Three-stating the data and address buses and the PMS, DMS, BMS, CMS, IOMS, RD, WR output drivers, Asserting the bus grant (BG) signal, and Halting program execution.
SYSTEM CONTROL REGISTER
15 0 14 0 13 0 12 0 11 0 10 1 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 1 1 1 0 1 DM (0x3FFF) PWAIT PROGRAM MEMORY WAIT STATES BMS ENABLE 0 = ENABLED, 1 = DISABLED
SPORT0A/SPORT0B ENABLED 1 = ENABLED, 0 = DISABLED SPORT1 ENABLED 1 = ENABLED, 0 = DISABLED 1 = SERIAL PORT 0 = FI, FO, IRQ0, IRQ1, SCLK
Figure 9. System Control Register
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If Go Mode is enabled, the modem processor will not halt program execution until it encounters an instruction that requires an external memory access. If a modem processor is performing an external memory access when an external device asserts the BR signal, it will not threestate the memory interfaces or assert the BG signal until the processor cycle after the access completes. The instruction does not need to be completed when the bus is granted. If a single instruction requires two external memory accesses, the bus will be granted between the two accesses. When the BR signal is released, the processor releases the BG signal, reenables the output drivers and continues program execution from the point where it stopped. The bus request feature operates at all times, including when the processor is booting and when RESET is active. The BGH pin is asserted when a modem processor is ready to execute an instruction, but is stopped because the external bus is already granted to another device. The other device can release the bus by deasserting bus request. Once the bus is released, the modem processor deasserts BG and BGH and executes the external memory access. When the ADSP-21MOD970 is powered up, all the modem processors must relinquish bus control, and only one processor at a time may control the bus.
Flag I/O Pins
ICE-PORT CONNECTOR GND 1 EBG 3 EBR 5 KEY 7 ELOUT 9 EE 11 12 ERESET 13 14 RESET 10 EMS 8 ECLK 6 ELIN 4 EINT BG1 BR1 RESET1 EE1 BG2 BR2 RESET2 EE2 BG3 BR3 RESET3 EE3 BG4 BR4 RESET4 EE4 BG5 BR5 RESET5 EE5 2 BR BG
of its memory mode. Therefore, it is vital that the mode pins are set correctly PRIOR to issuing a chip reset command from the emulator user interface. As the mode pins share functionality with PF0:3 on the ADSP-21MOD970, it may be necessary to reset the target hardware separately to insure the proper mode selection state on emulator chip reset. See the ADSP-2100 Family EZ-Tools data sheet for complete information on ICE products. The ICE-Port interface consists of the following ADSP-21MOD970 pins: EBR EBG ERESET EMS EINT ECLK ELIN ELOUT EE
These ADSP-21MOD970 pins must be connected only to the EZ-ICE connector in the target system. These pins have no function except during emulation, and do not require pull-up or pull-down resistors. The traces for these signals between the ADSP-21MOD970 and the connector must be kept as short as possible, no longer that 3 inches.
ADSP-21 mod970
ELOUT EBR EBG EINT ELIN ECLK EMS ERESET BG0 BR0 RESET0 EE0
Each modem processor has eight general purpose programmable input/output flag pins. They are controlled by two memory mapped registers. The PFTYPE register determines the direction, 1 = output and 0 = input. The PFDATA register is used to read and write the values on the pins. Data being read from a pin configured as an input is synchronized to the ADSP21mod970's clock. Bits that are programmed as outputs will read the value being output. The PF pins default to input during reset. In addition to the programmable flags, each modem processor has three fixed-mode output flags, FL0, FL1, and FL2. Note: Pins PF0, PF1, PF2 and PF3 are also used for device configuration during reset.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The ADSP-21MOD970 has on-chip emulation support and an ICE-Port, a special set of pins that interface to the EZ-ICE. These features allow in-circuit emulation without replacing the target system processor by using only a 14-pin connection from the target system to the EZ-ICE. Target systems must have a 14-pin connector to accept the EZ-ICE's in-circuit probe, a 14-pin plug. The EZ-ICE can emulate only one modem processor at a time. You must include hardware to select which processor in the ADSP-21MOD970 you want to emulate. Figure 10 is a functional representation of the modem processor selection hardware. You can use one ICE-Port connector with two ADSP-21MOD970 processors without using additional buffers. Issuing the "chip reset" command during emulation causes the modem processor to perform a full chip reset, including a reset BR
Figure 10. Selecting a Modem Processor in the ADSP-21MOD970
The following pins are also used by the EZ-ICE: BG RESET GND The EZ-ICE uses the EE (emulator enable) signal to take control of the ADSP-21MOD970 in the target system. This causes the processor to use its ERESET, EBR and EBG pins instead of the RESET, BR and BG pins. The BG output is three-stated. These signals do not need to be jumper-isolated in a system.
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The EZ-ICE connects to target system via a ribbon cable and a 14-pin female plug. The female plug is plugged onto the 14-pin connector (a pin strip header) on the target board.
Target Board Connector for EZ-ICE Probe
this data sheet. The performance of the EZ-ICE may approach published worst case specification for some memory access timing requirements and switching characteristics. Note: If your target does not meet the worst case chip specification for memory access parameters, you may not be able to emulate your circuitry at the desired CLKIN frequency. Depending on the severity of the specification violation, you may have trouble manufacturing your system as processor components statistically vary in switching characteristic and timing requirements within published limits. Restriction: All memory strobe signals on the ADSP-21MOD970 (RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in your target system must have 10 k pull-up resistors connected when the EZ-ICE is being used. The pull-up resistors are necessary because there are no internal pull-ups to guarantee their state during prolonged three-state conditions resulting from typical EZ-ICE debugging sessions. These resistors may be removed at your option when the EZ-ICE is not being used.
Target System Interface Signals
The EZ-ICE connector (a standard pin strip header) is shown in Figure 11. This connector must be added to the target board design if the EZ-ICE is to be used. Be sure to allow enough room in the system to fit the EZ-ICE probe onto the 14-pin connector.
GND EBG EBR KEY (NO PIN) ELOUT EE RESET BG BR EINT ELIN ECLK EMS ERESET
Figure 11. Target Board Connector for EZ-ICE
The 14-pin, 2-row pin strip header is keyed at the Pin 7 location--you must remove Pin 7 from the header. The pins must be 0.025 inch square and at least 0.20 inch in length. Pin spacing should be 0.1 x 0.1 inches. The pin strip header must have at least 0.15 inch clearance on all sides to accept the EZ-ICE probe plug. Pin strip headers are available from vendors such as 3M, McKenzie, and Samtec.
Target Memory Interface
When the EZ-ICE board is installed, the performance on some system signals changes. Design your system to be compatible with the following system interface signal changes introduced by the EZ-ICE board: * EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the processor on the RESET signal. EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the processor on the BR signal. EZ-ICE emulation ignores RESET and BR when singlestepping. EZ-ICE emulation ignores RESET and BR when in Emulator Space (processor halted). EZ-ICE emulation ignores the state of target BR in certain modes. As a result, the target system may take control of the processor's external memory bus only if bus grant (BG) is asserted by the EZ-ICE board's processor.
*
For your target system to be compatible with the EZ-ICE emulator, it must comply with the memory interface guidelines listed below.
PM, DM, BM, IOM, and CM
* * *
Design the Program Memory (PM), Data Memory (DM), Byte Memory (BM), I/O Memory (IOM) and Composite Memory (CM) external interfaces to comply with worst case device timing requirements and switching characteristics as specified in
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ADSP-21MOD970-SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade Parameter VDD TAMB Min 3.15 0 Max 3.45 +70 Unit V C
ELECTRICAL CHARACTERISTICS
Parameter VIH VIH VIL VOH Hi-Level Input Voltage Hi-Level CLKIN Voltage Lo-Level Input Voltage1, 3 Hi-Level Output Voltage1, 4, 5
1, 2
Test Conditions @ VDD = max @ VDD = max @ VDD = min @ VDD = min IOH = -0.5 mA @ VDD = min IOH = -100 A6 @ VDD = min IOL = 2 mA @ VDD = max VIN = VDD max @ VDD = max VIN = 0 V @ VDD = max VIN = VDD max8 @ VDD = max VIN = 0 V8 @ VDD = 3.3 tCK = 19 ns10 tCK = 25 ns10 tCK = 30 ns10 @ VDD = 3.3 TAMB = +25C tCK = 19 ns10 tCK = 25 ns10 tCK = 30 ns10 @ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = +25C @ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = +25C
Min 2.0 2.2
K/B Grades Typ Max
Unit V V V V V
0.8 2.4 VDD - 0.3 0.4 10 10 10 10 62 53 47
VOL IIH IIL IOZH IOZL IDD
Lo-Level Output Voltage1, 4, 5 Hi-Level Input Current3 Lo-Level Input Current3 Three-State Leakage Current7 Three-State Leakage Current7 Supply Current (Idle)9
V A A A A A mA mA mA
IDD
Supply Current (Dynamic)11
387 299 253 40
mA mA mA pF
CI CO
Input Pin Capacitance6 Output Pin Capacitance6, 7, 12
40
pF
NOTES 1 Bidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1-A13, PF0-PF7. 2 Input only pins: RESET, BR, DR0, DR1, PWD. 3 Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD. 4 Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH. 5 Although specified for TTL outputs, all ADSP-21MOD970 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads. 6 Guaranteed but not tested. 7 Three-statable pins: A0-A13, D0-D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1. 8 0 V on BR. 9 Idle refers to ADSP-21MOD970 state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND. 10 VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section. 11 IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 12 Output pin capacitance is the capacitive load for any three-stated output pin. Specifications subject to change without notice.
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ABSOLUTE MAXIMUM RATINGS* MEMORY TIMING SPECIFICATIONS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +4.6 V Input Voltage . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Output Voltage Swing . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Storage Temperature Range . . . . . . . . . . . . -65C to +150C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table VI shows common memory device specifications and the corresponding ADSP-21MOD970 timing parameter.
Table VI. Memory Devices and Timing Parameters
Memory Device Specification Address Setup to Write Start Address Setup to Write End Address Hold Time Data Setup Time Data Hold Time OE to Data Valid Address Access Time
ADSP21mod970 Timing Parameter tASW tAW tWRA tDW tDH tRDD tAA
Timing Parameter Definition A0-A13, xMS Setup before WR Low A0-A13, xMS Setup before WR Deasserted A0-A13, xMS Hold before WR Low Data Setup before WR High Data Hold after WR High RD Low to Data Valid A0-A13, xMS to Data Valid
TIMING PARAMETERS
GENERAL NOTES
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add up parameters to derive longer times.
TIMING NOTES
Switching characteristics specify how the processor changes its signals. You have no control over this timing--circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the processor will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices.
Note: xMS = PMS, DMS, BMS, CMS, IOMS.
FREQUENCY DEPENDENCY FOR TIMING SPECIFICATIONS
tCK is defined as 0.5 tCKI. The ADSP-21MOD970 uses an input clock with a frequency equal to half the instruction rate: a 26.32 MHz input clock (which is equivalent to 38.0 ns) yields a 19 ns processor cycle (equivalent to 52 MHz). tCK values within the range of 0.5 tCKI period should be substituted for all relevant timing parameters to obtain the specification value. Example: tCKH = 0.5 tCK - 7 ns = 0.5 (19 ns) - 7 ns = 2.5 ns
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating: TAMB TJ PD JA = = = = TJ - (PD x JA) Junction Temperature in C Power Dissipation in W Thermal Resistance (Junction-to-Ambient) Package PBGA
JA
26.9C/W
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21MOD970 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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POWER DISSIPATION CAPACITIVE LOADING
To determine total power dissipation in a specific application, the following equation should be applied for each output: C x VDD2 x f C = load capacitance, f = output switching frequency.
Figures 13 and 14 show the capacitive loading characteristics of the ADSP-21MOD970.
20 18
RISE TIME (0.4V - 2.4V) - ns
T = +85 C VDD = +3.0V
16 14 12 10 8 6
POWER, INTERNAL
1600 1537.2
1400 3.6V 1277.1
POWER - mW
1200 3.3V 1000 1008 3.0V 800 834.9 1029
4 0 50 100 CL - pF
52 FREQUENCY - MHz
150
200
250
678 600 33.3
Figure 13. Typical Output Rise Time vs. Load Capacitance, CL (at Maximum Ambient Operating Temperature)
10
250
POWER, IDLE
223.2 204.6 186 169.2
VDD = 3.6V
POWER - mW
200
VDD = 3.3V
VALID OUTPUT DELAY OR HOLD - ns
8 6
4 2
150
155.1 141
VDD = 3.0V
NOMINAL
100 33.33 FREQUENCY - MHz 52
-2 -4
POWER, IDLE n MODES
210 190 170 204.6 IDLE
0
40
80 CL - pF
120
160
200
POWER - mW
155.1
150 130 110 90 82.4076 70 79.2 33.33 FREQUENCY - MHz 86.3709 83.0709 IDLE (16) IDLE (128) 52
Figure 14. Typical Output Valid Delay or Hold vs. Load Capacitance, CL (at Maximum Ambient Operating Temperature)
Figure 12. Power vs. Frequency
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TEST CONDITIONS Output Disable Time
Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The output disable time (tDIS) is the difference between tMEASURED and tDECAY, as shown in Figure 15. The time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 V from the measured output high or low voltage. The decay time, tDECAY, is dependent on the capacitive load, CL, and the current load, iL, on the output pin. It can be approximated by the following equation:
t DECAY CL x 0.5 V = iL
output has reached a specified high or low trip point, as shown in Figure 16. If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.
REFERENCE SIGNAL
tMEASURED
VOH (MEASURED) OUTPUT VOL (MEASURED)
tDIS
VOH (MEASURED) -0.5V VOL (MEASURED) +0.5V
tENA
VOH (MEASURED) 2.0V 1.0V VOL (MEASURED) OUTPUT STARTS DRIVING
tDECAY
OUTPUT STOPS DRIVING
HIGH IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
from which tDIS = tMEASURED - tDECAY is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop driving.
INPUT OR OUTPUT
Figure 16. Output Enable/Disable
IOL
1.5V
1.5V
TO OUTPUT PIN
+1.5V 50pF
Figure 15. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
Output Enable Time
IOH
Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. The output enable time (tENA) is the interval from when a reference signal reaches a high or low voltage level to when the
Figure 17. Equivalent Device Loading for AC Measurements (Including All Fixtures)
REV. 0
-17-
ADSP-21MOD970 TIMING PARAMETERS
Parameter Clock Signals and Reset Timing Requirements: CLKIN Period tCKI tCKIL CLKIN Width Low tCKIH CLKIN Width High Switching Characteristics: tCKL CLKOUT Width Low tCKH CLKOUT Width High tCKOH CLKIN High to CLKOUT High Control Signals Timing Requirements: tRSP RESET Width Low tMS Mode Setup before RESET High tMH Mode Setup after RESET High 5 tCK1 2 5 ns ns ns 38 15 15 0.5 tCK - 7 0.5 tCK - 7 0 100 ns ns ns ns ns ns Min Max Unit
20
NOTE 1 Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time).
tCKI tCKIH
CLKIN
tCKIL tCKOH tCKH
CLKOUT
tCKL
PF(3:0)*
tMS
RESET
tMH
*PF3 IS MODE D, PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A
Figure 18. Clock Signals
-18-
REV. 0
ADSP-21MOD970
Parameter Interrupts and Flags Timing Requirements: IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4 tIFS tIFH IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4 Switching Characteristics: tFOH Flag Output Hold after CLKOUT Low5 tFOD Flag Output Delay from CLKOUT Low5 0.25 tCK + 15 0.25 tCK 0.25 tCK - 7 0.5 tCK + 6 ns ns ns ns Min Max Unit
NOTES 1 If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the ADSP-2100 Family User's Manual, Third Edition, for further information on interrupt servicing.) 2 Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced. 3 IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE. 4 PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7. 5 Flag outputs = PFx, FL0, FL1, FL2, Flag_out.
tFOD
CLKOUT
tFOH
FLAG OUTPUTS
tIFH
IRQx FI PFx
tIFS
Figure 19. Interrupts and Flags
REV. 0
-19-
ADSP-21MOD970 TIMING PARAMETERS
Parameter Bus Request-Bus Grant Timing Requirements: tBH BR Hold after CLKOUT High1 tBS BR Setup before CLKOUT Low1 Switching Characteristics: tSD CLKOUT High to xMS, RD, WR Disable tSDB xMS, RD, WR Disable to BG Low tSE BG High to xMS, RD, WR Enable xMS, RD, WR Enable to CLKOUT High tSEC tSDBH xMS, RD, WR Disable to BGH Low2 tSEH BGH High to xMS, RD, WR Enable2 0.25 tCK + 2 0.25 tCK + 17 0.25 tCK + 10 0 0 0.25 tCK - 4 0 0 ns ns ns ns ns ns ns ns Min Max Unit
NOTES xMS = PMS, DMS, CMS, IOMS, BMS. 1 BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User's Manual, Third Edition, for BR/BG cycle relationships. 2 BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS BMS, RD WR
tSD
tSEC
BG
tSDB
tSE
BGH
tSDBH
tSEH
Figure 20. Bus Request-Bus Grant
-20-
REV. 0
ADSP-21MOD970
Parameter Memory Read Timing Requirements: tRDD RD Low to Data Valid tAA A0-A13, xMS to Data Valid tRDH Data Hold from RD High Switching Characteristics: tRP RD Pulsewidth tCRD CLKOUT High to RD Low tASR A0-A13, xMS Setup before RD Low A0-A13, xMS Hold after RD Deasserted tRDA tRWR RD High to RD or WR Low
w = wait states x tCK. xMS = PMS, DMS, CMS, IOMS, BMS.
Min
Max
Unit
0.5 tCK - 9 + w 0.75 tCK - 12.5 + w 0 0.5 tCK - 5 + w 0.25 tCK - 5 0.25 tCK - 6 0.25 tCK - 3 0.5 tCK - 5
ns ns ns ns ns ns ns ns
0.25 tCK + 7
CLKOUT
A0-A13 DMS, PMS, BMS, IOMS, CMS
tRDA
RD
tASR tCRD
D
tRP
tRWR
tAA
WR
tRDD
tRDH
Figure 21. Memory Read
REV. 0
-21-
ADSP-21MOD970 TIMING PARAMETERS
Parameter Memory Write Switching Characteristics: Data Setup before WR High tDW Data Hold after WR High tDH tWP WR Pulsewidth tWDE WR Low to Data Enabled A0-A13, xMS Setup before WR Low tASW tDDR Data Disable before WR or RD Low tCWR CLKOUT High to WR Low A0-A13, xMS, Setup before WR Deasserted tAW tWRA A0-A13, xMS Hold after WR Deasserted tWWR WR High to RD or WR Low
w = wait states x tCK. xMS = PMS, DMS, CMS, IOMS, BMS.
Min
Max
Unit
0.5 tCK - 7 + w 0.25 tCK - 2 0.5 tCK - 5 + w 0 0.25 tCK - 6 0.25 tCK - 7 0.25 tCK - 5 0.75 tCK - 9 + w 0.25 tCK - 3 0.5 tCK - 5
0.25 tCK + 7
ns ns ns ns ns ns ns ns ns ns
CLKOUT
A0-A13 DMS, PMS, BMS, CMS, IOMS
tWRA
WR
tASW tAW tCWR
D
tWP tDH
tWWR tDDR
tDW tWDE
RD
Figure 22. Memory Write
-22-
REV. 0
ADSP-21MOD970
Parameter Serial Ports Timing Requirements: tSCK SCLK Period tSCS DR/TFS/RFS Setup before SCLK Low tSCH DR/TFS/RFS Hold after SCLK Low SCLKIN Width tSCP Switching Characteristics: tCC CLKOUT High to SCLKOUT tSCDE SCLK High to DT Enable SCLK High to DT Valid tSCDV tRH TFS/RFSOUT Hold after SCLK High tRD TFS/RFSOUT Delay from SCLK High DT Hold after SCLK High tSCDH tTDE TFS (Alt) to DT Enable tTDV TFS (Alt) to DT Valid SCLK High to DT Disable tSCDD tRDV RFS (Multichannel, Frame Delay Zero) to DT Valid 38 4 7 15 0.25 tCK 0 0 15 0 0 14 15 15 0.25 tCK + 10 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min Max Unit
CLKOUT
tCC
tCC tSCP tSCS tSCH
tSCK
SCLK
tSCP
DR TFSIN RFSIN
tRD tRH
RFSOUT TFSOUT
tSCDV tSCDE
DT
tSCDD tSCDH
tTDE tTDV
TFSOUT
ALTERNATE FRAME MODE
tRDV
RFSOUT
MULTICHANNEL MODE, FRAME DELAY 0 (MFD = 0)
tTDE tTDV
TFSIN
ALTERNATE FRAME MODE
tRDV
RFSIN
MULTICHANNEL MODE, FRAME DELAY 0 (MFD = 0)
Figure 23. Serial Ports
REV. 0
-23-
ADSP-21MOD970 TIMING PARAMETERS
Parameter IDMA Address Latch Timing Requirements: Duration of Address Latch1, 2 tIALP tIASU IAD15-0 Address Setup before Address Latch End2 IAD15-0 Address Hold after Address Latch End2 tIAH tIKA IACK Low before Start of Address Latch2, 3 tIALS Start of Write or Read after Address Latch End1, 2 tIALD Address Latch Start after Address Latch End1, 2
NOTES 1 Start of Address Latch = IS Low and IAL High. 2 End of Address Latch = IS High or IAL Low. 3 Start of Write or Read = IS Low and IWR Low or IRD Low.
Min
Max
Unit
10 5 2 0 3 2
ns ns ns ns ns ns
IACK
tIKA
IAL
tIALD tIALP tIALP
IS
IAD15-0
tIASU
tIAH
tIASU
tIAH tIALS
RD OR WR
Figure 24. IDMA Address Latch
-24-
REV. 0
ADSP-21MOD970
Parameter IDMA Write, Short Write Cycle Timing Requirements: tIKW IACK Low before Start of Write1 tIWP Duration of Write1, 2 tIDSU IAD15-0 Data Setup before End of Write2, 3, 4 IAD15-0 Data Hold after End of Write2, 3, 4 tIDH Switching Characteristic: tIKHW Start of Write to IACK High
NOTES 1 Start of Write = IS Low and IWR Low. 2 End of Write = IS High or IWR High. 3 If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH. 4 If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH.
Min
Max
Unit
0 15 5 2 4 15
ns ns ns ns ns
tIKW
IACK
tIKHW
IS
tIWP
IWR
tIDSU
IAD15-0 DATA
tIDH
Figure 25. IDMA Write, Short Write Cycle
REV. 0
-25-
ADSP-21MOD970 TIMING PARAMETERS
Parameter IDMA Write, Long Write Cycle Timing Requirements: tIKW IACK Low before Start of Write1 IAD15-0 Data Setup before IACK Low2, 3, 4 tIKSU tIKH IAD15-0 Data Hold after IACK Low2, 3, 4 Switching Characteristics: tIKLW Start of Write to IACK Low4 tIKHW Start of Write to IACK High 0 0.5 tCK + 10 2 1.5 tCK 4 ns ns ns ns ns Min Max Unit
15
NOTES 1 Start of Write = IS Low and IWR Low. 2 If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH. 3 If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH. 4 This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User's Manual, Third Edition.
tIKW
IACK
tIKHW tIKLW
IS
IWR
tIKSU
IAD15-0 DATA
tIKH
Figure 26. IDMA Write, Long Write Cycle
-26-
REV. 0
ADSP-21MOD970
Parameter IDMA Read, Long Read Cycle Timing Requirements: tIKR IACK Low before Start of Read1 tIRK End of Read after IACK Low2 Switching Characteristics: IACK High after Start of Read1 tIKHR tIKDS IAD15-0 Data Setup before IACK Low tIKDH IAD15-0 Data Hold after End of Read2 tIKDD IAD15-0 Data Disabled after End of Read2 tIRDE IAD15-0 Previous Data Enabled after Start of Read tIRDV IAD15-0 Previous Data Valid after Start of Read tIRDH1 IAD15-0 Previous Data Hold after Start of Read (DM/PM1)3 tIRDH2 IAD15-0 Previous Data Hold after Start of Read (PM2)4
NOTES 1 Start of Read = IS Low and IRD Low. 2 End of Read = IS High or IRD High. 3 DM read or first half of PM read. 4 Second half of PM read.
Min
Max
Unit
0 2 4 0.5 tCK - 7 0 0 10 2 tCK - 5 tCK - 5 15
ns ns ns ns ns ns ns ns ns ns
10
IACK
tIKR
IS
tIKHR
tIRK
IRD
tIRDE
IAD15-0 PREVIOUS DATA
tIKDS
READ DATA
tIKDH
tIRDV tIRDH
tIKDD
Figure 27. IDMA Read, Long Read Cycle
REV. 0
-27-
ADSP-21MOD970 TIMING PARAMETERS
Parameter IDMA Read, Short Read Cycle Timing Requirements: tIKR IACK Low before Start of Read1 tIRP Duration of Read Switching Characteristics: tIKHR IACK High after Start of Read1 IAD15-0 Data Hold after End of Read2 tIKDH tIKDD IAD15-0 Data Disabled after End of Read2 tIRDE IAD15-0 Previous Data Enabled after Start of Read tIRDV IAD15-0 Previous Data Valid after Start of Read
NOTES 1 Start of Read = IS Low and IRD Low. 2 End of Read = IS High or IRD High.
Min
Max
Unit
0 15 4 0 0 10 15 10
ns ns ns ns ns ns ns
IACK
tIKR
IS
tIKHR
tIRP
IRD
tIRDE
IAD15-0 PREVIOUS DATA
tIKDH
tIRDV
tIKDD
Figure 28. IDMA Read, Short Read Cycle
-28-
REV. 0
ADSP-21MOD970
304-Ball PBGA Package Pinout
The ADSP-21MOD970 package pinout is shown in the table below. Ball Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 Signal Name GND PF0_1 PF2_1 FL1_1 D23_1 D21_1 D13_1 D16_1 GND PF0_2 PF1_2 FL0_2 FL1_2 VDD VDD PF0_3 PF1_3 FL0_3 FL1_3 D21 D22 D23 GND IAD3_1 GND PF1_1 FL0_1 D22_1 D20_1 D19_1 D15_1 GND D14_1 BGH_2 PF3_2 FL2_2 VDD VDD BGH_3 PF2_3 PF3_3 FL2_3 D20 DT0A GND Ball Number B23 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 Signal Name IAD1 IAD5_1 IAD0_1 GND BGH_1 PF3_1 FL2_1 D12_1 D17_1 GND IAD13_1 IAD15_1 PF2_2 VDD VDD VDD IS_2 CLKOUT_2 PF4_2 DT1_2 EE_2 GND IAD2 IAD0 IAD6_1 IAD4_1 A0_1 GND D10_1 D11_1 D9_1 D18_1 GND IAD14_1 BR_1 BG_1 IACK_1 VDD VDD BG_2 BR_2 PF5_2 RESET_2 GND GND Ball Number D22 D23 E1 E2 E3 E4 E20 E21 E22 E23 F1 F2 F3 F4 F20 F21 F22 F23 G1 G2 G3 G4 G20 G21 G22 G23 H1 H2 H3 H4 H20 H21 H22 H23 J1 J2 J3 J4 J20 J21 J22 J23 K1 K2 K3 Signal Name IAD4 IAD3 IAD8_1 IAD7_1 IAD2_1 IAD1_1 CLKIN GND GND GND IAD12_1 IAD9_1 IAD10_1 IWR_1 GND GND GND GND CLKIN_1 IAD11_1 D8_1 IRD_1 IAL IRD IWR GND RD_1 WR_1 IAL_1 IS_1 CLKOUT_3 RFS0A DR0A IS_3 DMS_1 BMS_1 PMS_1 CLKOUT_1 SCLK0A PF4_3 BG_3 BR_3 D19 PF4_1 IOMS_1 Ball Number K4 K20 K21 K22 K23 L1 L2 L3 L4 L20 L21 L22 L23 M1 M2 M3 M4 M20 M21 M22 M23 N1 N2 N3 N4 N20 N21 N22 N23 P1 P2 P3 P4 P20 P21 P22 P23 R1 R2 R3 R4 R20 R21 R22 R23 Signal Name CMS_1 PF5_3 EBG EBR EINT D17 D18 PF5_1 PF7_1 VDD ERESET ELIN ELOUT D15 D16 PF6_1 BGH_4 VDD VDD VDD VDD D13 D12 D14 PF1_4 VDD PF6_3 ECLK EMS GND GND GND TFS0_1 DT1_3 PF2_6 RESET_3 EE_3 IAD6 IAD7 IAD5 PF0_4 PF0_6 PF1_6 FL2_6 FL1_6
REV. 0
-29-
ADSP-21MOD970
304-Ball PBGA Package Pinout (continued)
Ball Number T1 T2 T3 T4 T20 T21 T22 T23 U1 U2 U3 U4 U20 U21 U22 U23 V1 V2 V3 V4 V20 V21 V22 V23 W1 W2 W3 W4 W20 W21 W22
Signal Name D10 D9 D11 EE_1 BGH_6 TFS0_3 PF3_6 FL0_6 IAD9 IAD11 IAD8 PF2_4 GND GND GND GND IAD10 IAD12 DT1_1 PF3_4 GND GND GND GND D8 CLKOUT_4 RESET_1 IS_4 IS_6 PF7_3 IAD15
Ball Number W23 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 AA1 AA2 AA3 AA4 AA5 AA6 AA7
Signal Name GND VDD VDD VDD GND FL0_4 VDD FL2_4 CLKOUT_5 GND IS_5 VDD TFS0_2 PF6_2 PF0_5 FL0_5 FL2_5 RFS1 SCLK1 GND GND BR_5 IAD13 IACK PF4_4 BG_4 GND GND FL1_4 VDD EE_4
Ball Number AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15
Signal Name PF4_5 GND PF6_5 VDD DT1_5 BGH_5 PF7_2 PF1_5 FL1_5 TFS1 DR1 GND DT1_6 GND BG_5 IAD14 PF5_4 GND PF6_4 GND DT1_4 VDD RESET_4 PF5_5 GND PF7_5 VDD RESET_5 PF4_6 GND PF3_5
Ball Number AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23
Signal Name PF2_5 CLKOUT_6 RFS0B GND SCLK0B RESET_6 GND BG_6 GND BR_4 PF7_4 GND TFS0_4 VDD VDD GND GND TFS0_5 VDD EE_5 PF5_6 GND PF6_6 PF7_6 DT0B TFS0_6 GND DR0B EE_6 BR_6 GND
ORDERING GUIDE
Part Number ADSP-21MOD970-000
RELATED DOCUMENTS
Ambient Temperature Range 0C to +70C
Processor Clock 26.0 MHz
Package Description 304-Ball PBGA
Package Option B-304
ADSP-21MOD970-110 Multiport Internet Gateway Processor solution.
-30-
REV. 0
REV. 0
4 14 VDD VDD VDD VDD IS 2 PF4 2 PF5 2 RESET 2 GND CLKIN GND IAL CLK OUT 3 SCLK0A PF5 3 VDD DT1 2 BG 2 BR 2 EE_2 VDD CLK OUT 2 BGH 3 PF2 3 PF3 3 FL2 3 D20 DT0A GND GND GND GND IRD RFS0A PF4 3 EBG ERESET VDD VDD DT1 3 PF0 6 BGH 6 GND GND IS 6 FL0 4 VDD VDD GND GND GND 9 TFS0 5 10 PF7 5 VDD VDD VDD 7 8 GND 6 RESET 4 PF5 5 EE 4 PF4 5 PF6 5 VDD VDD VDD 11 GND VDD FL1 4 DT1 4 TFS0 4 5 FL2 4 CLK OUT 5 IS 5 TFS0 2 DT1 5 RESET 5 EE 5 12 PF6 2 BGH 5 PF4 6 PF5 6 13 PF0 5 PF7 2 GND GND 14 FL0 5 PF1 5 PF3 5 PF6 6 15 FL2 5 FL1 5 PF2 5 PF7 6 16 RFS1 TFS1 CLK OUT 6 DT0B 17 SCLK1 DR1 RFS0B TFS0 6 18 GND GND GND GND 19 GND DT1 6 VDD PF6 3 PF2 6 PF1 6 TFS0 3 GND GND PF7 3 BR 5 GND SCLK0B RESET 6 DR0B 20 EE 6 21 PF0 3 VDD VDD VDD PF1 3 FL0 3 FL1 3 D21 D22 15 D23 1 D22 1 PF3 1 FL2 1 D11 1 D9 1 D18 1 GND 1AD14 1 BR 1 BG 1 IACK 1 D12 1 D17 1 IAD13 1 PF2 2 D10 1 GND IAD15 1 VDD D20 1 D19 1 D15 1 GND D14 1 PF3 2 FL2 2 BGH 2 D21 1 D13 1 D16 1 GND PF1 2 FL0 2 FL1 2 PF0 2 5 6 7 8 10 11 12 13 16 17 18 19 9 20 21 22 D23 GND IAD2 IAD4 GND GND IWR DR0A BG 3 EBR ELIN VDD ECLK RESET 3 FL2 6 PF3 6 GND GND IAD15 IAD13 BG 5 GND BR 6 22 23 GND IAD1 IAD0 IAD3 GND GND GND IS 3 BR 3 EINT ELOUT VDD EMS EE 3 FL1 6 FL0 6 GND GND GND IACK IAD14 BG GND 23 A B C D E F G H J K L M N P R T U V W Y AA AB AC GND IS 1
PIN
1
2
3
A
GND
PF0 1
PF2 1
FL1 1
B
IAD3 1
GND
PF1 1
FL0 1
C
IAD5 1
IAD0 1
GND
BGH 1
D
IAD6 1
IAD4 1
A0 1
E
IAD8 1
IAD7 1
IAD2 1
IAD1 1
F
IAD12 1
IAD9 1
IAD10 1
IWR 1
G
CLKIN 1
IAD11 1
D8 1
IRD 1
H
RD 1
WR 1
IAL 1
J
DMS 1
BMS 1
PMS 1
CLK OUT 1
K
D19
PF4 1
IOMS 1
CMS 1
L
D17
D18
PF5 1
PF7 1
M
D15
D16
PF6 1
BGH 4
ADSP-21MOD970
(TOP VIEW)
ADSP-21MOD970 Pinout
-31-
IS 4 GND GND GND GND 4
N
D13
D12
D14
PF1 4
P
GND
GND
GND
TFS0 1
R
IAD6
IAD7
IAD5
PF0 4
T
D10
D9
D11
EE 1
U
IAD9
IAD11
IAD8
PF2 4
V
IAD10
IAD12
DT1 1
PF3 4
W
D8
CLK OUT 4
RESET 1
Y
VDD
VDD
VDD
AA
PF4 4
BG 4
GND
AB
PF5 4
GND
PF6 4
AC
GND
BR 4
PF7 4
1
2
3
ADSP-21MOD970
NOTE: THE NUMBER AFTER THE UNDERSCORE IN SIGNAL NAMES CORRESPONDS TO THE MODEM CHANNEL NUMBER IN THE FUNCTIONAL BLOCK DIAGRAM ON PAGE 1. ANY SIGNAL NAME WITHOUT AN UNDERSCORE CORRESPONDS TO SIGNALS BEING SHARED AMONG MODEM CHANNELS NUMBER 2-6.
ADSP-21MOD970
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
304-Ball Metric Plastic Ball Grid Array (B-304)
1.224 (31.10) 1.220 (31.00) SQ 1.217 (30.90)
0.050 (1.27) BSC 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A B C D E F G H J K L M N P R T U V W Y AA AB AC
TOP VIEW
1.104 (28.04) 1.100 (27.94) 1.096 (27.84)
BOTTOM VIEW
1.051 (26.70) 1.037 (26.35) SQ 1.024 (26.00) 0.100 (2.54) 0.092 (2.33) 0.083 (2.12)
0.050 (1.27) BSC DETAIL A
1.104 (28.04) 1.100 (27.94) 1.096 (27.84)
DETAIL A
0.024 (0.62) 0.022 (0.56) 0.020 (0.50) 0.048 (1.22) 0.046 (1.17) 0.044 (1.12)
NOTE 1. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.012 (0.30) OF THE IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. 2. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.004 (0.10) OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID. 3. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
0.008 (0.20) 0.035 (0.90) 0.028 (0.70) SEATING MAX 0.024 (0.60) PLANE 0.030 (0.75) 0.024 (0.60) 0.020 (0.50) BALL DIAMETER
-32-
REV. 0
PRINTED IN U.S.A.
C3494-2.5-7/99

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